High Throughput Two- Dimensional Median Filters On FPGA for Image Processing Applications
نویسندگان
چکیده
An efficient hardware implementation of a median filter is presented. Input samples are used to construct a cumulative histogram, which is then used to find the median. The resource usage of the design is independent of window size, but rather, dependent on the number of bits in each input sample. This offers a realizable way of efficiently implementing large-windowed median filtering, as required by transforms such as the Trace Transform. The method is then extended to weighted median filtering. The Median filter is an effective method for the removal of impulse-based noise from the images. This paper suggests an optimized architecture for filter implementation on FPGA. A 3x3 sliding window algorithm is used as the base for filter operation. Partial implementation is done via soft core processor. The designs are synthesized for a Xilinx Spartan-3
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